72 macrocells, 10 ns — right-sizing the glue logic
The XC9572XL-10VQG44C is a 72-macrocell CPLD from the XC9500XL series, packing 1600 usable gates and 34 I/O into a 44-VQFP package. The 10 ns pin-to-pin propagation delay (tpd) means combinatorial decisions propagate through the fabric in one clock edge at up to 100 MHz — fast enough to latch address decoding, bus arbitration, or state-machine transitions without adding wait states.
In-system programmable — instant-on, non-volatile
This CPLD is in-system programmable with a minimum of 10,000 program/erase cycles per macrocell. The non-volatile flash fabric holds the configuration at power-up — no external configuration PROM, no boot time. It is instant-on the moment the supply rail hits 3.0 V. For a board that needs to sequence power rails or decode chip selects before the main processor releases reset, the instant-on characteristic eliminates the window where an FPGA would still be loading its SRAM bitstream.
34 I/O in a 44-VQFP — board integration
The 44-VQFP (10x10 mm body, 0.8 mm pitch) routes out 34 user I/O. The fine-pitch QFP demands a 4-layer board for clean fan-out on the inner rows, but the package is standard and well-supported by common footprint libraries. Surface-mount assembly with the tray packaging — no tape-and-reel, so the part ships in anti-static trays suitable for prototype runs and low-to-medium volume production.