36 macrocells, 10 ns pin-to-pin — the glue-logic fit
The XC9536XL-10VQG44C is a 36-macrocell CPLD from the XC9500XL series, packing 800 gates in a 44-VQFP package with 34 user I/O. The 10 ns pin-to-pin propagation delay (tpd) sets the ceiling for combinatorial paths through the device — at 100 MHz system clock, a single LUT level plus routing fits within one cycle, but two-level logic cascaded across macrocells starts to eat into setup margin. For address decoding, bus bridging, or state-machine control in a 3.3 V system, this delay class keeps the timing closure straightforward without needing a faster speed grade.
In-system programmable — 10K cycle floor
The device is in-system programmable with a minimum endurance of 10,000 program/erase cycles. That endurance floor covers field-update scenarios — firmware rollouts over the product lifetime won't wear out the configuration cells. The IEEE 1532 JTAG interface handles the programming; no separate high-voltage rail is needed.
44-VQFP — board-fit checklist
The 44-VQFP (10x10 mm body, 0.8 mm pitch) is a standard fine-pitch QFP. The exposed pad is not present — thermal dissipation goes through the leads and the package body. The 34 I/O plus dedicated JTAG pins (TDI, TDO, TMS, TCK) and power/ground fill the 44 positions. Decoupling: one 0.1 µF ceramic per VCC pin pair, placed within 5 mm of the pin, keeps the core switching noise below the 200 mV peak-to-peak guideline. The 0.8 mm pitch routes cleanly on a two-layer board with 6/6 mil trace/space rules.
Active lifecycle, RoHS3 — sourcing posture
For a 3.3 V glue-logic design with a 10 ns timing budget, this is a stable, in-production choice with no near-term obsolescence risk.