AMD (Xilinx) C67402AN — Logic ICs
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AMD (Xilinx) / Logic ICs

C67402AN FIFO 64x5 Asynchronous 40ns 16-DIP

MPN C67402AN
End of Life Spot Stock · 24-48h Dispatch 100% Original Sealed

C67402AN, asynchronous FIFO, 64 x 5 memory size, 40 ns access time, 15 MHz data rate, 4.75 V to 5.25 V supply, 0 °C to 70 °C, 16-PDIP, Bulk.

In Stock: 1,181 pcs
MOQ: 1 pcs
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[SPEC] Essential Parameters Snapshot Full Specifications (15)
Package / Case 16-DIP
Supply Voltage 4.75 V ~ 5.25 V
Memory / RAM 64 x 5

Full Technical Specifications

15 Parameters
C67402AN specifications
Parameter / AttributeSpecification / Value
MountingThrough Hole
Expansion typeWidth
Supply voltage4.75 V ~ 5.25 V
Current - supply190mA
Operating temperature0°C ~ 70°C
PackageBulk
FunctionAsynchronous
Data rate15MHz
Access time40ns
Memory size64 x 5
FWFT supportNo
Case16-DIP
Bus directionalUni-Directional
Retransmit capabilityNo
Programmable flags supportNo
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Technical Details & Description

64 x 5 asynchronous FIFO in a 16-DIP footprint

The C67402AN is a 64-word by 5-bit asynchronous FIFO with a 15 MHz data rate and 40 ns access time.

The 40 ns access time is 5 ns faster than the sibling C67402N (45 ns). That extra margin matters when the host processor's read strobe is tight or when you're running near the 15 MHz data-rate ceiling. The C67401AN shares the same 40 ns access time but is 64 x 4 wide — one bit narrower. If your data path is 5 bits wide, the C67402AN is the correct width; dropping to the 4-bit variant would require a second device or software packing.

Where it fits — and where it doesn't

It is not rated for industrial motor drives or outdoor enclosures. The 190 mA maximum supply current is drawn from the 5 V rail; size the 5 V regulator for that peak plus any additional loads on the same bus. Expansion is width-only (cascading for wider words, not deeper FIFO depth), so if you need more than 64 words, look at a deeper FIFO family or a different architecture.

Frequently asked questions

What is the access time of C67402AN?

The C67402AN has a 40 ns access time. That is the time from the read-enable assertion to valid data on the output pins.

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