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Abracon LLC ASEMB-33.330MHZ-LR — Crystals & Oscillators

Abracon ASEMB-33.330MHZ-LR XO

MPNASEMB-33.330MHZ-LR
Active

Abracon LLC ASEMB Pure Silicon™ XO oscillator, 33.33 MHz, CMOS output, 1.8–3.3 V, ±25ppm, MEMS resonator, 4-SMD 3.20×2.50mm, standby function, -40°C~85°C.

Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

ASEMB-33.330MHZ-LR specifications
ParameterValue
TypeXO (Standard)
SeriesASEMB, Pure Silicon™
MountingSurface Mount
Supply voltage1.8V ~ 3.3V
Current - supply16mA
Current - supply (Disable)15µA
Frequency33.33 MHz
Frequency stability±25ppm
Operating temperature-40°C~85°C
Size (Dimension)0.126\" L x 0.098\" W (3.20mm x 2.50mm)
Height - seated0.035\" (0.90mm)
OutputCMOS
PackageTape & Reel (TR)
FunctionStandby (Power Down)
Base resonatorMEMS
Case4-SMD, No Lead

Product details

What the MEMS resonator changes for your clock tree

The ASEMB-33.330MHZ-LR is a CMOS-output XO (Standard) using a MEMS resonator rather than an AT-cut crystal — the base resonator entry lists MEMS as the source. This shifts the shock and vibration profile decisively: MEMS resonators have no piezoceramic fracture risk and maintain frequency under mechanical stress that would stress-grain a crystal. For portable or industrial equipment where the board sees >50 g shock, the MEMS base is the primary selection driver, not a footnote. The tradeoff is that MEMS oscillators typically carry slightly higher phase noise floor than high-Q crystal XOs at offsets beyond 1 MHz — if the 33.33 MHz clock feeds a PLL or clock cleaner, verify the phase-noise mask against the MEMS plot before committing the BOM line.

33.33 MHz and the supply rails — what fits this clock

The 33.33 MHz frequency is a non-trivial clock choice — 33.333... MHz is the 5th submultiple of the 166.666... MHz USB High-Speed reference, and it also appears as a divide-down target in Ethernet PHY clock trees and some CAN FD designs. The ±25ppm frequency stability meets Ethernet 100BASE-TX tolerance (±50 ppm total) and satisfies most UART and sensor bus clock requirements without a trim register.

Standby pin and the power budget

The standby (power-down) function is the key power-management feature on this part. When asserted, the oscillator draws ≤15 µA maximum, compared to 16 mA maximum in normal operation — roughly a 1000× reduction. A battery-powered node that needs the clock only during active sampling or burst transmission can gate the ASEMB rather than letting a continuously-running crystal oscillator burn 16 mA between events. The 15 µA disable figure is the floor to design against; the actual current in a powered-off state is what the downstream logic sees as load, so verify the upstream rail can tolerate that residual draw if the supply stays energized during standby.

Footprint and the 3.2 × 2.5 mm package for dense layouts

The ultra-low profile makes it viable under daughtercards or alongside tall connectors; the no-lead frame calls out a thermal pad land pattern — confirm the layout uses the manufacturer-recommended landing pad and solder mask opening, because MEMS oscillator paste reflow profiles are more sensitive to voiding than standard crystal packages. Standard surface-mount pick-and-place handling applies — no special co-planarity concerns with this package style.

Frequently asked questions

What is the ASEMB-33.330MHZ-LR used for in a typical design?

The 33.33 MHz output typically serves as a reference clock for USB High-Speed PHY divide-down paths, Ethernet PHY subsystems, or CAN FD controllers — anywhere a sub-50 ppm clock at CMOS levels fits the rail. The standby function makes it equally viable for battery-scheduled nodes where the clock is gated between measurement or transmission bursts.

Does the ASEMB-33.330MHZ-LR require any external support components beyond supply decoupling?

No additional external components are listed as required — the oscillator is a self-contained clock source. Standard practice is a 100 nF bypass cap as close as possible to the supply pins, and keeping the output trace short enough that the CMOS edge does not couple into adjacent high-impedance nodes. The 1.8–3.3 V supply range is single-rail; no negative bias or dual-rail staging is needed.