The 20ns typical rise and 15ns typical fall times mean the switching transition losses in the driven FET are dominated by the gate charge, not the driver's own edge rate. Two independent channels let you drive a synchronous buck's high-side and low-side FETs from separate PWM paths, or parallel both channels for an 8A effective peak into a single large gate.
Supply range and logic thresholds — rail compatibility
The supply range spans 4V to 15V, covering the common 5V and 12V bias rails found in automotive ECUs and industrial power supplies. The logic input thresholds are set at 1V (VIL) and 2V (VIH), so the driver accepts 3.3V logic from a microcontroller or PWM controller without a level shifter — the 2V VIH is comfortably below a 3.3V logic-high output. Both inverting and non-inverting input options are available per channel, giving flexibility to match the polarity of the upstream controller without adding an external inverter.
This part carries AEC-Q100 qualification, the automotive industry's stress-test standard for integrated circuits. The 125°C ceiling is the absolute junction temperature limit for most automotive-grade MOSFETs, so the driver's own thermal margin is not the constraint — the FET's Rds(on) derating at 125°C will set the current limit.
Package and footprint — 8-SOIC layout notes
The 0.154-inch (3.90mm) width means the pin pitch is the usual 1.27mm SOIC pitch — no fine-pitch challenges. For a 4A peak driver, place the bypass capacitor (typically 1µF ceramic) within 5mm of the VDD and GND pins to keep the high-frequency loop inductance low; the fast 20ns edges will ring on a long supply trace.
Sourcing and lifecycle — active production
The base product number is UCC27425, and the QDRQ1 suffix denotes the automotive-qualified, tape-and-reel variant.