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UCC27323DRG4

UCC27323DRG4 Low-Side MOSFET Driver, 4A Peak, -55°C to 150°C

MPNUCC27323DRG4
End of Life

Texas Instruments UCC27323DRG4, dual low-side MOSFET gate driver, 4A peak output source and sink, 20ns rise / 15ns fall typ, 4.5V to 15V supply, inverting inputs, independent channels, -55°C to 150°C operating temperature, 8-SOIC package.

Texas Instruments UCC27323DRG4 datasheet (PDF)
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

UCC27323DRG4 specifications
ParameterValue
Gate typeN-Channel, P-Channel MOSFET
Input typeInverting
Channel typeIndependent
MountingSurface Mount
Supply voltage4.5V ~ 15V
Logic voltage - VIL, VIH1V, 2V
Current - peak output (Source, sink)4A, 4A
Operating temperature-55°C~150°C(TJ)
PackageTape & Reel (TR)
Case8-SOIC (0.154\", 3.90mm Width)
Number of drivers2
Driven configurationLow-Side
Rise (Fall time)20ns, 15ns

Product details

Dual 4A low-side driver with military temperature range

It drives both N-channel and P-channel MOSFETs with independent, inverting inputs. The 20ns typical rise time and 15ns typical fall time keep switching losses low in power converters and motor drives.

Operates from 4.5V to 15V supply, covering standard 5V and 12V gate drive rails. Logic thresholds are 1V (VIL) and 2V (VIH), making it directly compatible with 3.3V and 5V PWM controllers without level shifting.

The surface-mount footprint matches standard SOIC-8 land patterns.

Frequently asked questions

How does UCC27323DRG4 compare to UCC27324?

The UCC27324 is the non-inverting version of the same dual 4A low-side driver family. Both share the same pinout, supply range, output drive, and SOIC-8 package. The only difference is the input polarity: UCC27323DRG4 has inverting inputs, UCC27324 has non-inverting inputs. Choose based on your PWM controller's output polarity.

Is UCC27323DRG4 compatible with 5V logic?

Yes. The logic thresholds are 1V (VIL) and 2V (VIH), so 3.3V and 5V logic levels drive it directly without external level translation.