The 8 ns typical rise time and 7 ns fall time at 1 nF load keep switching losses low enough that the designer can push the switching frequency into the hundreds of kilohertz without the driver becoming the thermal bottleneck. The bootstrap supply supports a high-side rail up to 120 V, which covers 48 V bus converters, 72 V telecom bricks, and 100 V intermediate bus architectures with margin.
Supply rails and logic thresholds — fitting the bias architecture
The driver operates from a single 8 V to 17 V bias rail, which matches the standard 12 V or 15 V auxiliary supply found in most power converters. The logic input thresholds are 0.8 V (VIL) and 2.5 V (VIH), so a 3.3 V PWM controller output drives the inputs directly without a level-shifter. The non-inverting input type means the output follows the input polarity — no inversion to account for in the control loop.
Thermal and package — the PowerPad matters for the current loop
The surface-mount footprint is the same 3.90 mm width as a standard SOIC-8, but the pad pattern differs; the PCB layout must include the exposed-paddle land.
The SO PowerPad package is a standard TI footprint, and the part shares the same die and pinout as the rest of the UCC27201 family, differing only in the package variant.