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Texas Instruments TPS7A1119PYKAR — Power Management (PMIC / Gate Driver)

TPS7A1119PYKAR 500mA LDO, 2.6µA Iq, 5-DSBGA

MPNTPS7A1119PYKAR
End of Life

Texas Instruments TPS7A1119PYKAR low-VIN LDO, 500 mA output, 1.9 V fixed, 2.6 µA quiescent, 5-XFBGA DSBGA package, active production.

$1.2Ref. price · indicative, final on quote
Packaging5-XFBGA, DSBGA
RoHSROHS3 Compliant
Sourced new & surplus through independent channelsAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

TPS7A1119PYKAR specifications
ParameterValue
Output typeFixed
MountingSurface Mount
Voltage - input3.3V
Voltage dropout0.11V @ 500mA
Voltage - output (Min (Fixed))1.9V
Output current500mA
Current - supply11 µA
Current - quiescent2.6 µA
Operating temperature-40°C ~ 125°C (TJ)
PSRR64dB ~ 35dB (1kHz ~ 1.5MHz)
PackageTape & Reel (TR); Cut Tape (CT)
Case5-XFBGA, DSBGA
Control featuresEnable
Protection featuresOver Current, Over Temperature, UVLO
Number of regulators1
Output configurationPositive

Product details

500 mA LDO with 2.6 µA quiescent — the load and standby budget

The TPS7A1119PYKAR is a 500 mA low-dropout linear regulator from Texas Instruments, fixed 1.9 V output, in a 5-pin DSBGA package. Its 2.6 µA quiescent current makes it suited for battery-powered or always-on subsystems where the regulator's own draw must stay below the system's sleep budget. Maximum dropout is 110 mV at the full 500 mA load, meaning the input rail must stay at least 110 mV above 1.9 V across the load range to maintain regulation. The 3.3 V maximum input voltage confirms this is a low-VIN LDO designed for sub-3.3 V rails — not for 5 V or 12 V intermediate buses.

PSRR profile — noise rejection across the switching band

Power-supply rejection ratio is specified at 64 dB at 1 kHz, rolling off to 35 dB at 1.5 MHz. This profile matters when the LDO follows a switching regulator: the 64 dB at 1 kHz catches the fundamental ripple of a typical 400 kHz–1 MHz buck converter, but the 35 dB at 1.5 MHz means high-frequency switching harmonics above 1 MHz pass through with less attenuation. A downstream LC filter or a second LDO stage may be needed for noise-sensitive analog loads.

Junction temperature range and protection

The protection suite includes overcurrent, overtemperature, and undervoltage lockout — the UVLO prevents the output from sourcing current into a shorted or pre-biased load during startup. The enable pin allows the regulator to be gated by a system supervisor or GPIO, pulling the quiescent current to near zero when the load is shut down.

Frequently asked questions

What is the PSRR of TPS7A1119PYKAR at 1 kHz?

PSRR is 64 dB at 1 kHz, rolling to 35 dB at 1.5 MHz. This profile attenuates switching-regulator ripple in the 400 kHz–1 MHz band but passes higher-frequency harmonics with less rejection.

What package does TPS7A1119PYKAR use?

The 0.4 mm pitch and 0.5 mm body height require a controlled reflow profile and X-ray inspection for solder-joint verification.