Texas Instruments TPS74301RGWT — Power Management (PMIC / Gate Driver)
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Texas Instruments / Power Management (PMIC / Gate Driver)

TPS74301RGWT LDO, 1.5A, 73dB PSRR, 20-VQFN

MPN TPS74301RGWT
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Texas Instruments TPS74301RGWT adjustable LDO, 1.5 A output, 73 dB ~ 42 dB PSRR (1 kHz ~ 800 kHz), 0.12 V dropout at 1.5 A, 20-VQFN Exposed Pad, surface mount.

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[SPEC] Essential Parameters Snapshot Full Specifications (17)
Package / Case 20-VQFN Exposed Pad

Full Technical Specifications

17 Parameters
TPS74301RGWT specifications
Parameter / AttributeSpecification / Value
Output typeAdjustable
MountingSurface Mount
Voltage - input5.5V
Voltage dropout0.12V @ 1.5A
Voltage - output3.6V
Voltage - output (Min (Fixed))0.8V
Output current1.5A
Current - supply1.5 mA
Current - quiescent115 µA
Operating temperature-40°C ~ 125°C
PSRR73dB ~ 42dB (1kHz ~ 800kHz)
PackageTape & Reel (TR); Cut Tape (CT)
Case20-VQFN Exposed Pad
Control featuresEnable, Power Good, Tracking
Protection featuresOver Current, Over Temperature, Short Circuit, Under Voltage Lockout (UVLO)
Number of regulators1
Output configurationPositive
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Technical Details & Description

The TPS74301RGWT delivers 73 dB of power-supply rejection at 1 kHz, rolling off to 42 dB at 800 kHz. For a noise-sensitive load — a VCO supply, an ADC reference, or a SerDes PLL — this PSRR profile determines how much upstream switching ripple bleeds into the output. The 73 dB floor at 1 kHz knocks a 10 mVpp ripple down to roughly 2 µVpp at the load; above 800 kHz the rejection drops, so a downstream LC filter ahead of the LDO is worth budgeting for if the switcher runs above 1 MHz.

120 mV dropout at 1.5 A — headroom planning

Maximum dropout is 120 mV at the full 1.5 A load. If the input rail is a nominal 5.0 V that dips to 4.8 V during a transient, the LDO still holds regulation down to 3.6 V output — but a 3.3 V rail from that same 4.8 V input leaves only 1.5 V headroom, well above the dropout ceiling. The headroom margin is the input-to-output differential minus the dropout; budget at least 200 mV of margin across temperature and load to stay out of dropout. Quiescent current is 115 µA typical, rising to 1.5 mA max under full load. That 115 µA ground current is low enough for battery-powered always-on domains — a sensor node that sleeps at 10 µA system draw sees the LDO's Iq as the dominant idle load, so a load-switch on the LDO input is worth considering for sub-mA sleep modes.

Control features include Enable, Power Good, and Tracking. The Tracking pin lets the output follow an external reference ramp during power-up — useful for sequencing core and I/O rails in FPGAs that specify monotonic rise and a maximum slew rate. Power Good asserts when the output reaches ~92% of the nominal voltage, giving the downstream load a reset release signal.

20-VQFN exposed pad — thermal and board integration

The 20-VQFN (5x5 mm) package with an exposed pad requires a thermal land on the PCB. Protection features include over-current, over-temperature, short-circuit, and under-voltage lockout (UVLO). The UVLO threshold typically sits at 1.35 V rising, so the LDO stays off until the input rail is above that level — preventing the output from tracking a brown-out input. The over-temperature shutdown trips at ~165°C typical, with 15°C of hysteresis.

Frequently asked questions

Where can I buy TPS74301RGWT and how is it quoted?

The TPS74301RGWT is sourced through independent distribution channels. Submit an RFQ for a firm quote with lead time.

What is the PSRR of TPS74301RGWT at 1 kHz?

PSRR is 73 dB at 1 kHz, rolling off to 42 dB at 800 kHz. This means a 10 mVpp ripple at 1 kHz on the input is attenuated to roughly 2 µVpp at the output.

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