Dual fixed-output LDO with sequenced power-up
The TPS70148PWP from Texas Instruments integrates two positive-output LDO regulators in a single 20-pin HTSSOP package, delivering fixed 3.3V at 500mA and 1.5V at 250mA from a maximum 6V input rail. The dual-channel architecture with enable, power-good, reset, and sequencing control features makes it suited for powering split-rail ASICs, FPGAs, or DSPs that require a defined power-up order between the core and I/O supplies.
PSRR and noise rejection at 1 kHz
With 60dB PSRR at 1kHz, the regulator attenuates switching noise from a downstream DC-DC converter by a factor of 1000 — critical for keeping the analog supply rail clean in mixed-signal designs where the converter ripple falls in the audio or low-frequency band. The 190 µA quiescent current and 230 µA maximum supply current keep the overhead low for always-on rails in battery-powered instrumentation.
Industrial temperature range and package thermal management
The 0.28V maximum dropout at 500mA on the 3.3V rail means the input must stay above 3.58V to maintain regulation at full load — a 5V rail with 10% tolerance (4.5V min) provides sufficient headroom.
Protection and control feature set
Built-in overcurrent, overtemperature, reverse polarity, and undervoltage lockout (UVLO) protection cover the common fault modes in a single-supply system — the UVLO threshold prevents the output from turning on until the input rail is stable, eliminating the need for an external supervisor on the input. The sequencing control allows the 1.5V core rail to ramp after the 3.3V I/O rail with a programmable delay, matching the power-up sequence required by many FPGA and processor datasheets.
Active lifecycle and compliance status
Fully RoHS3 compliant and free of the six restricted substances plus the four phthalates — no exemption declarations needed for EU-market equipment shipping after July 2019.