3.3V rail supervisor with a 170 ms reset hold
When the supply drops below the threshold, the active-low, open-drain output asserts and holds the reset state for a minimum of 170 ms after the rail returns. That 170 ms window gives the system oscillator and PLLs time to stabilise before the processor starts fetching code — nominal is not absolute max, so budget the minimum value, not a typical, when sizing the capacitor on the delay pin. The open-drain output lets you wire-OR the reset signal with other supervisors or a manual reset button, pulling it high with an external resistor to the logic supply.
What the 170 ms timeout means for the board
The 170 ms minimum reset timeout is the period the supervisor holds the processor in reset after VDD crosses the rising threshold. That duration is long enough to let a typical quartz oscillator or ceramic resonator reach stable amplitude and frequency before the CPU starts executing. If your system uses a fast-starting MEMS oscillator, you might be tempted to use a shorter timeout part, but the 170 ms window also covers bulk decoupling capacitors charging up — a point often missed in the timing budget.