Voltage supervisor for 1.8V core rails
Its open-drain output allows direct connection to a microcontroller reset pin or wired-OR with other fault signals, and the reset timeout is adjustable via an external capacitor, giving the designer control over power-up sequencing.
The 1.8V threshold is set for monitoring low-voltage core supplies common in modern FPGAs, SoCs, and DSPs. When the monitored rail falls below this level, the reset output goes active low, holding the system in reset until the supply recovers and the adjustable timeout period expires. This prevents the processor from attempting to execute code during a brownout or slow power-up.
Open-drain output and adjustable timeout
The open-drain output can be pulled up to any voltage up to the absolute maximum of the pin, allowing the supervisor to interface with 3.3V or 5V logic without a level shifter. The adjustable reset timeout is set with a single capacitor — a common practice for matching the reset hold time to the power supply's rise time or the system clock's stabilization period.