3.07V threshold supervisor for 3.3V rails
The reset timeout is adjustable via an external capacitor, giving the designer control over the hold-off period before the processor is released from reset.
Military temperature range — the deployment envelope
Adjustable reset timeout — one cap sets the delay
Instead of a fixed timeout, the TPS3808G33MDBVREP lets you program the reset pulse width by selecting a capacitor value on the CT pin. This is useful when the downstream MCU or FPGA needs a specific hold-off time to stabilise its internal regulators or oscillators before the reset de-asserts. The same BOM line can cover a 1.25 ms delay for a fast-starting Cortex-M0 or a 200 ms delay for a larger SoC with a PLL lock time — just change the capacitor, not the supervisor part number.
SOT-23-6 footprint and open-drain output
Housed in a 6-pin SOT-23 package, this supervisor takes up minimal board area — about 3 mm × 3 mm. The open-drain output lets you wire-OR the reset signal with other supervisors or a manual reset button, pulling the line low from any source. The output requires a pull-up resistor to the logic supply rail (typically 10 kΩ to 100 kΩ). Because the output is open drain, it can be pulled up to a different voltage than the monitored rail, which is handy when the supervisor monitors a 3.3V rail but the processor's reset input runs at 1.8V.