2.33V threshold supervisor in SOT-23-6
The TPS3808G25DBVTG4: When the monitored voltage drops below that level, the active-low, open-drain output asserts reset and holds it for an adjustable timeout period before releasing.
Adjustable reset timeout — why it matters on the BOM
The reset timeout is adjustable/selectable via an external capacitor, so you can set the delay to match the power-up ramp of the downstream MCU, FPGA, or SoC. A too-short timeout risks the core starting before the supply is stable; a too-long timeout delays system readiness. This part lets you tune that window without changing the supervisor IC. The open-drain output allows wired-OR connection with other reset sources, and the active-low polarity matches the reset input of most microcontrollers and digital processors.