Two-rail supervisor in a 5-pin SC-70
The active-low reset output is open-drain, so it can be wire-ORed with other reset signals on the board. The minimum reset timeout is 100 µs, which is short enough to avoid delaying the system start-up but long enough to ride through a brief brown-out on the rail.
What the 100 µs reset timeout buys you
The 100 µs minimum reset timeout means the supervisor holds the reset line low for at least that long after both monitored voltages rise above their thresholds. That pulse width is enough to let the power supply rails stabilise and the oscillator start before the processor tries to execute code. If your system has a slow-starting LDO or a large bulk capacitor on the 3 V rail, verify that the 100 µs window is sufficient — otherwise the processor may wake up before the rail is fully settled.
Adjustable threshold — one channel, no fixed limit
The second monitored channel is adjustable via an external resistor divider, so you are not locked into a standard threshold. The fixed 3 V channel covers the common 3.3 V rail with a nominal 3 V threshold, giving about 300 mV of margin below 3.3 V before a reset is triggered.
SC-70-5 — small footprint, layout considerations
The SC-70-5 (SOT-353) package measures roughly 2.0 mm × 2.1 mm, which fits in tight spaces on a multi-rail board. The 0.65 mm pin pitch is fine for a two-layer PCB with careful routing, but the open-drain output needs a pull-up resistor to the monitored rail or to the system's I/O voltage.