The three monitored channels have fixed thresholds at 2.25 V and 2.93 V, plus a third adjustable input set with an external resistor divider. Both active-high and active-low reset outputs are available on the same chip, so you can drive a processor's reset pin and an FPGA's enable input without extra logic. The push-pull totem-pole output stage sinks or sources current directly, eliminating the need for a pull-up resistor on the active-low line.
Threshold voltages and reset timing
The 2.25 V threshold is sized for a 2.5 V core rail, and the 2.93 V threshold covers a 3.3 V I/O supply. The adjustable channel lets you monitor a third rail at any voltage above 1.25 V using two resistors — typical targets are 1.8 V, 5.0 V, or a battery voltage. When any monitored voltage drops below its threshold, the reset outputs assert immediately. After all rails recover above threshold, the reset timeout holds the outputs low for a minimum of 140 ms before releasing. That delay gives the processor's oscillator and PLL time to stabilise before the first instruction fetch.
For volume production or a BOM line that needs dual sourcing, the base number TPS3307 covers the whole family of threshold variants.