Dual-voltage supervisor for two-rail systems
It is designed for systems that need a single IC to sequence and protect a dual-voltage power domain — typical in DSPs, FPGAs, and mixed-signal boards where a 1.8V core and a 2.9V/3.3V I/O rail coexist.
The two monitored thresholds are 1.85V and 2.92V. The 1.85V threshold is sized for a nominal 1.8V core supply with about 50 mV of guardband below the regulated level; a dip below 1.85V triggers a reset. The 2.92V threshold covers a nominal 3.0V or 3.3V rail — it trips before the rail drops far enough to cause logic corruption. The reset output is open-drain, active low, so multiple supervisors can wire-OR their outputs to a shared reset line without contention.
Reset timing — 70 ms minimum timeout
Once all monitored voltages rise above their thresholds, the TPS3306-20D holds the reset output low for a minimum of 70 ms before releasing it. This timeout gives the system power supplies and oscillators time to stabilise before the processor or FPGA starts executing code. The 70 ms figure is a minimum — the actual timeout will be longer at lower temperatures or with supply tolerances, so the system should be designed to tolerate at least that window.
The 8-SOIC footprint is common and well-supported by PCB design libraries.