Dual-rail voltage monitor — 1.4 V and 2.93 V thresholds
The TPS3306-15DGK: The reset output is open-drain, allowing multiple supervisors to share a common pull-up resistor in a wired-OR configuration — useful for sequencing multiple power domains in an FPGA or mixed-signal board. A minimum reset timeout of 70 ms holds the system in reset long enough for all regulated rails to stabilize after a brownout or power-up event before the processor begins executing code.
Industrial temperature grade and 8-VSSOP package
The 8-VSSOP package (also designated 8-TSSOP or 8-MSOP with 0.118-inch, 3.00 mm width) sits on a 0.65 mm pitch — a standard fine-pitch footprint that routes cleanly on a two-layer board with proper ground plane under the package.
The part is supplied in tube packaging; for reel or tape-and-reel quantities, confirm the ordering code suffix with the distributor at quote time.
