Texas Instruments TPS3126E15DBVT, Simple Reset/Power-On Reset, Active Low, Open Drain Output, 1.43V Threshold, 100ms Minimum Reset Timeout, SOT-23-5, -40°C to 85°C.
| Parameter | Value |
|---|---|
| Type | Simple Reset/Power-On Reset |
| Mounting | Surface Mount |
| Voltage - threshold | 1.43V |
| Number of voltages monitored | 1 |
| Operating temperature | -40°C~85°C(TA) |
| Reset | Active Low |
| Output | Open Drain or Open Collector |
| Package | Tape & Reel (TR); Cut Tape (CT) |
| Reset timeout | 100ms Minimum |
| Case | SC-74A, SOT-753 |
The reset output remains low for a minimum of 100 ms after the monitored voltage rises above the threshold, providing a clean power-on reset pulse for the downstream processor or logic.
The 100 ms minimum reset timeout gives the downstream processor time to stabilise its internal regulators and clock before the reset is released, which is standard for most MCUs and FPGAs.
The reset timeout is a minimum of 100 ms. After the monitored voltage rises above the 1.43 V threshold, the reset output stays low for at least that duration before releasing.
Yes, the reset output is active low. The output goes low when the monitored voltage falls below the 1.43 V threshold and stays low through the 100 ms timeout period after recovery.