1.08V threshold supervisor in a SOT-23-5
It combines both Active High and Active Low reset outputs in a push-pull, totem pole configuration, giving the designer flexibility to interface with either polarity of downstream logic without an external inverter.
100 ms reset timeout — what it buys the system
The minimum 100 ms reset timeout gives the power supply and oscillator time to stabilize before the processor or FPGA is released from reset. For a typical MCU with a 10 ms startup window, the 100 ms period provides margin across temperature and supply ramp rate without requiring an external delay capacitor. The SOT-23-5 package keeps the footprint small enough for space-constrained designs like sensor nodes or distributed power modules.
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