200 MHz dual-core DSP for real-time control
Flash and RAM — what fits where
The 1 MB Flash is organized as 512K x 16, which is the full program store for a dual-core firmware image. The RAM, at 102K x 16, is shared between the two C28x cores. For a dual-loop motor-drive or digital power supply, the control-law accelerator and the main core each need their own scratchpad; the linker script must partition the RAM explicitly. The bootloader sits in a dedicated ROM sector and does not steal from the 1 MB Flash — one less thing to chase in the linker map.
