It runs at 100 MHz with a single-core C28x DSP-optimized architecture, 128 KB of Flash program memory, and 26K x 16 of RAM.
The 16-channel 12-bit ADC, triggered by the PWM module without CPU intervention, samples all three phase currents plus DC-link voltage in a single PWM cycle. The DMA engine moves the results directly to RAM — the core stays free to run the control law.
Lifecycle reality — obsolete, sourced through independent channels
Peripheral set — what connects where
The 88 GPIOs are muxed with these peripherals — the pin assignment in the 176-BGA package determines which functions are available simultaneously. Plan the pin-multiplexing allocation before layout: the CAN and SPI pins share a port with some of the PWM outputs, so a motor-drive design that needs three CAN nodes and six PWM channels may require careful signal routing.
Package note — 176-BGA (15x15 mm)
The 176-ball BGA requires a controlled soldering profile and X-ray inspection for voiding and solder-ball shorts. The 15x15 mm body is compact for the I/O count.