90 MHz C28x core — control-loop headroom
The 90 MHz clock gives the C28x integer core enough cycles to execute a full PID loop with feedforward terms and still leave margin for communications stack overhead. Program memory is 256 KB of on-chip Flash, backed by 50K x 16 of RAM — enough for a moderate application firmware image and a double-buffered data array for ADC results or comms packets.
Peripheral set for motor-control and industrial comms
The 12-channel, 12-bit ADC (A/D 12x12b) is sized for three-phase current sensing plus auxiliary voltage or temperature inputs. All 40 I/O are brought out to the 80-pin LQFP package (12x12 mm body), surface-mount only.
Temperature range and supply rails
Internal oscillator is available, though an external clock or crystal can be used for tighter timing on the CAN or PWM.