At 60 MHz the C28x core executes a single-cycle 32-bit multiply-accumulate, so a 10 kHz current-control loop with sensor read, PI compensator, and PWM update fits in under 6 µs. That leaves headroom for CAN message handling and diagnostics without pushing the core to the wall. The F280041PZQR sibling runs at 100 MHz and adds a second 12-bit DAC and more ADC channels, but the 60 MHz part is the cost-optimized entry for designs that do not need the extra throughput.
64-TQFP footprint and supply rails
The 64-TQFP (10x10 mm) package with 33 I/O routes cleanly on a two-layer automotive board.