PSRR and noise rejection across the switching band
The TLV70525PYFPT delivers 80 dB PSRR at 10 kHz, rolling off to 55 dB at 1 MHz — this is the band where most DC-DC converter switching noise lives. For a 2.2 MHz buck converter feeding this LDO, the 55 dB rejection at the switching fundamental knocks the ripple down by a factor of ~560, keeping the output clean enough for sensitive analog front-ends. At 200 mA output, the maximum dropout voltage is only 0.25 V — the input rail needs just 2.75 V to maintain regulation. This headroom margin matters when the pre-regulator is a battery or a loosely regulated bus that sags under load.
Thermal envelope and protection suite
Built-in over-current, over-temperature, reverse polarity, and under-voltage lockout (UVLO) protection means the regulator can survive a faulted output or a reversed supply without external clamp diodes. The UVLO threshold prevents the output from turning on below the minimum input voltage, avoiding brown-out conditions on the load.
Quiescent draw and enable control
Quiescent current is 55 µA typical, rising to 315 µA maximum under full supply current. The enable pin lets the system designer shut down the regulator entirely when the load is idle — in shutdown the input current drops to leakage levels, extending battery life in intermittently-powered sensor nodes.