Four LVDS receivers in one 16-SOIC — what this means for your backplane
It takes four differential LVDS inputs and delivers four single-ended CMOS outputs.
TI lists the SN75LVDS390D as Active. That means no last-time-buy notice in effect, no EOL letter to chase.
200 Mbps per channel — the timing margin reality
At 200 Mbps the SN75LVDS390D handles 100 MHz clock or 200 Mb/s NRZ data on each of its four channels. The propagation delay and skew are tight enough for most parallel LVDS links up to about 12 to 18 inches of FR4 trace. If your link runs longer or you need >200 Mbps, you step to a faster receiver — but for the common 100 MHz–200 Mbps range this part is a direct fit. No external termination resistors needed if the driver side already has them; the receiver inputs are high impedance and rely on the driver's far-end termination.
Package and footprint — 16-SOIC with 0.154" body width
No exposed pad, no thermal vias to plan — just route the four differential pairs to pins 1–8 (inputs) and the four CMOS outputs on pins 9–16. The 3V to 3.6V range lets it run from a 3.3V rail with margin for ripple.