Eight LVDS receivers in a 38-TSSOP — what this part does
The Texas Instruments SN75LVDS388ADBTRG4 is an eight-channel LVDS receiver in a 38-TSSOP surface-mount package. It converts differential LVDS signals at the input side into single-ended CMOS-level outputs, supporting a per-channel data rate of 200 Mbps.
200 Mbps per channel — bus margin and signal integrity
The 200 Mbps data rate per receiver is the headline timing spec. In a typical LVDS link, that translates to a 5 ns unit interval. With the receiver's input threshold and propagation delay, you need to budget about 1.5 ns of the UI for the receiver itself, leaving roughly 3.5 ns for the cable, connector, and driver jitter. That's comfortable for short backplane traces up to a few meters, but for longer runs or higher noise environments you'll want to verify eye margin at the receiver input. The eight receivers share a common supply and ground, so simultaneous switching noise on the output side can couple back into the differential inputs if the layout doesn't keep the output bus away from the input pairs.
Obsolete — sourcing reality and the replacement question
The SN75LVDS388ADBTRG4 is listed as obsolete. For new designs, consider TI's current LVDS receiver portfolio which offers similar channel counts and data rates in smaller packages, though the pinout will differ.