Schmitt-trigger cleanup for noisy 5V rails
The SN74ACT14D is a hex inverter built on the 74ACT family, with Schmitt-trigger inputs that reject noise and slow edges on each of the six channels.
Timing and drive margins at 5V
Maximum propagation delay is 11.5 ns at 5 V with a 50 pF load — that is the worst-case window for signal settling across the six inverters. For a 10 MHz clock buffer, the 11.5 ns leaves under 88 ns of the period for the rest of the path, so verify the cumulative delay against your setup/hold requirements. Quiescent current maxes at 2 µA, so the part adds negligible static draw to a 5 V rail — useful in always-on sense circuits where every microamp counts. Input logic thresholds are asymmetric: low is 0.5 V to 1.4 V, high is 1.2 V to 2.1 V. That hysteresis window (~0.7 V typical) is what rejects the noise on a slowly rising sensor output or a long backplane trace.