RS-485 half-duplex transceiver in 8-SOIC — 500 kbps, 5 V supply
It handles one driver and one receiver on a shared differential bus, with a maximum data rate of 500 kbps.
Half-duplex constraint and bus timing
Because this is a half-duplex part, the driver and receiver share the same bus pair. The firmware must manage the driver enable (DE) and receiver enable (RE) pins to avoid contention — the bus turns around between transmit and receive cycles. At 500 kbps the bit period is 2 µs, so the enable-to-data timing needs to be accounted for in the UART driver state machine. The 130 mV hysteresis helps with slow edges on long stubs, but the half-duplex architecture is the primary fit constraint: if the application needs simultaneous bidirectional communication, this part won't work.