Supply range and input offset
The supply span is 10 V to 12 V — tight by modern standards, but deliberate: the voltage-feedback architecture optimises speed and noise at these rail voltages. Input offset voltage is 300 µV typical, and input bias current is 20 µA. That bias current is higher than a JFET or CMOS op-amp, so source impedance must be balanced in precision DC-coupled stages. For AC-coupled paths (transformer input, capacitive coupling), the bias current is less of a concern.
Package and mounting
SOT-23-5 footprint, same as many single op-amps. The pinout is standard for this package: non-inverting input, inverting input, V–, V+, output. Surface-mount only. Tape & Reel or Cut Tape options for prototype or production volume.