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Texas Instruments SN74LVC86APWR — Signal Isolation

SN74LVC86APWR XOR Gate, 14-TSSOP, 1.65-3.6V, 4.4ns

MPNSN74LVC86APWR
End of Life

Texas Instruments 74LVC series XOR (Exclusive OR) gate, SN74LVC86APWR, quad 2-input, 14-TSSOP package, 1.65V to 3.6V supply, 24mA output, 4.4ns propagation delay.

$0.49Ref. price · indicative, final on quote
Packaging14-TSSOP (0.173", 4.40mm Width)
RoHSROHS3 Compliant
Series74LVC
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

SN74LVC86APWR specifications
ParameterValue
Series74LVC
Logic typeXOR (Exclusive OR)
MountingSurface Mount
Supply voltage1.65V ~ 3.6V
Current - quiescent1 µA
Current - output high, low24mA, 24mA
I/O channels2
Operating temperature-40°C ~ 125°C
PackageTape & Reel (TR); Cut Tape (CT)
Case14-TSSOP (0.173\", 4.40mm Width)
Number of circuits4
Input logic level - low0.7V ~ 0.8V
Input logic level - high1.7V ~ 2V
Max propagation delay @ v, max CL4.4ns @ 3.3V, 50pF

Product details

Quad XOR in a 14-TSSOP footprint

The SN74LVC86APWR: Each gate performs the XOR function: output goes high when the two inputs differ, making it the go-to cell for data comparison, parity generation/checking, encryption datapath mixing, and phase-detection in PLL feedback loops.

Propagation delay and drive — what 4.4 ns and 24 mA mean on the bench

Maximum propagation delay is 4.4 ns at 3.3 V with a 50 pF load. That sets the usable toggle rate ceiling: with a 4.4 ns delay, the gate can cleanly pass a 100 MHz clock edge — but the actual system data rate depends on the cumulative delay through the XOR chain plus the output rise time into the downstream load. For a single-gate path, budget 4.4 ns tPD plus ~2 ns rise time (into 15 pF) for a safe 60-80 MHz throughput. Output sink and source both rated 24 mA — enough to drive a standard CMOS input fan-out of 10-15 loads without external buffers, or to directly switch an LED indicator through a series resistor. The symmetric drive also keeps the high-to-low and low-to-high transition times matched, which matters for maintaining duty cycle in clock distribution. Quiescent current sits at 1 µA max. In a battery-powered system that gates the XOR supply when idle, the standby drain is below the self-discharge rate of a CR2032 coin cell — no need for a separate load switch.

Temperature grade and voltage thresholds — where this part runs

An engine-bay ECU or a solar-inverter controller that sees 105°C ambient still has 20°C of margin before the junction hits the 125°C ceiling. Input logic thresholds are LVCMOS: low level 0.7 V to 0.8 V, high level 1.7 V to 2 V. At 3.3 V VCC, the high threshold is 1.7 V, so a 2.5 V CMOS output drives it cleanly. At 1.8 V VCC, the low threshold is 0.7 V — a 1.2 V output from a lower-voltage FPGA I/O bank may not guarantee a logic-low without a level translator.

Active production, no end-of-life signal

No official successor or second-source listed. The 74LVC family is mature and stable — the XOR function in this package has no direct pin-compatible drop-in from other manufacturers, so confirm the BOM position before committing the board.

Frequently asked questions

Is SN74LVC86APWR compatible with 5V logic?

Input thresholds are LVCMOS: high level 1.7 V to 2 V, low level 0.7 V to 0.8 V. Running at 5 V VCC exceeds the absolute maximum rating and will damage the device. For 5 V systems, use a 74HCT or 74AHCT series XOR gate instead.