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Texas Instruments LMK1D2106RHAT — Clock & Timing ICs

TI LMK1D2106RHAT Clock Buffer, 2 GHz, 2:6 Fanout, 40-VQFN

MPNLMK1D2106RHAT
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Texas Instruments LMK1D2106RHAT Clock Buffer, 2 GHz max frequency, 2:6 fanout, differential I/O, 40-VFQFN Exposed Pad, Tape & Reel.

$11.9009Ref. price · indicative, final on quote
Texas Instruments LMK1D2106RHAT datasheet (PDF)
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

LMK1D2106RHAT specifications
ParameterValue
TypeClock Buffer
MountingSurface Mount
Supply voltage1.71V ~ 1.89V, 2.375V ~ 2.625V, 3.135V ~ 3.465V
Frequency - max2 GHz
Operating temperature-40°C ~ 105°C (TA)
InputCML, HCSL, LVCMOS, LVDS, LVPECL
OutputClock, LVDS
PackageTape & Reel (TR)
Case40-VFQFN Exposed Pad
Number of circuits2
Ratio - Input:Output2:6
Differential - Input:OutputYes/Yes

Product details

High-speed clock distribution for 2 GHz signal chains

The LMK1D2106RHAT is a 2:6 clock buffer from Texas Instruments that fans out one or two input clocks to six LVDS outputs at up to 2 GHz — the rate needed for SERDES reference clocks, data converter sampling clocks, and FPGA transceiver fabric distribution. It accepts any of five common differential or single-ended standards — CML, HCSL, LVCMOS, LVDS, or LVPECL — so the same BOM line serves designs where the upstream oscillator or PLL output format is not yet frozen.

All six LVDS outputs are differential, so the PCB trace pair must be length-matched and impedance-controlled to 100 ohms differential to preserve signal integrity at 2 GHz edge rates.

Frequently asked questions

What is the LMK1D2106RHAT used for?

It is a 2:6 clock buffer that distributes a high-speed reference clock (up to 2 GHz) to six LVDS destinations — ADC/DAC sampling clocks, FPGA transceiver banks, or SERDES PLL reference inputs.

What input signal formats does the LMK1D2106RHAT accept?

It accepts CML, HCSL, LVCMOS, LVDS, and LVPECL — the five most common high-speed clock formats — so it bridges between an oscillator or clock generator and the downstream receivers without external level translation.