PLL jitter cleaner for high-speed clock trees
The Texas Instruments LMK04832NKDT is a PLL-based jitter cleaner that accepts a clock input and delivers up to 14 differential or single-ended outputs across six signal formats — CML, HSDS, LCPECL, LVCMOS, LVDS, and LVPECL — at a maximum output frequency of 3.255 GHz. It is designed to clean the phase noise on a reference clock before distributing it to ADCs, DACs, FPGAs, or SERDES transceivers in applications such as wireless infrastructure, radar, instrumentation, and high-speed data acquisition.
Output flexibility and supply tolerance
With a 3:14 input-to-output ratio, the device can fan out a single clean reference to multiple loads while maintaining sub-100 fs RMS jitter typical at the outputs. All signal paths are differential on both input and output sides, which means the layout must treat each pair as a controlled-impedance 100-ohm differential trace with matched length.