The Texas Instruments LMK04832NKDR is a PLL-based jitter cleaner designed to reduce phase noise on clock signals for high-speed data converters, SERDES, and RF sampling systems. It accepts a clock input and generates up to fourteen low-jitter outputs across six differential logic families: CML, HSDS, LCPECL, LVCMOS, LVDS, and LVPECL. The 3:14 input-to-output ratio means three clock inputs can be fanned out to fourteen device clocks, each independently configurable for frequency and output type. The maximum output frequency of 3.255 GHz covers the clocking needs of JESD204B ADCs and high-speed FPGAs.
3.255 GHz max frequency — where the clock tree ceiling sits
The 3.255 GHz upper limit is the synthesised output ceiling, not the PFD rate. This part is sized for the clock distribution of 12 GSPS ADCs and 28 Gbps SERDES lanes, where the reference clock runs at a fraction of the data rate. Below that ceiling, the jitter cleaner loop bandwidth is programmable to suppress close-in phase noise from the reference source. Supply voltage is 3.15 V to 3.45 V, a single 3.3 V rail with tight tolerance.
It is not qualified for automotive under-hood or extended military temperature ranges. The base product number is LMK04832; the NKDR suffix denotes the specific reel and package variant.