Dual-PLL jitter cleaner for high-speed clock trees
The LMK04821NKDT is a dual-PLL jitter cleaner from TI's PLLatinum™ family, designed to clean up noisy reference clocks and distribute them across a system. It accepts LVCMOS, LVDS, or LVPECL inputs and outputs HSDS, LCPECL, LVCMOS, LVDS, or LVPECL formats, covering the signal types used in ADC/DAC clocking, SerDes reference, and FPGA transceiver links. The 3:15 input-to-output ratio means three independent input references can be fanned out to fifteen outputs, which can eliminate external clock buffers in a multi-IC clock tree. The maximum output frequency of 1.54 GHz supports high-speed serial interfaces and RF sampling converters.
The supply voltage range of 3.15 V to 3.45 V means it runs from a 3.3 V rail with margin — confirm your regulator's tolerance stays within that window. All inputs and outputs are differential-capable, which is necessary for maintaining signal integrity at the 1.54 GHz ceiling. Single-ended LVCMOS is also supported for lower-speed distribution paths.
No official successor or second-source is listed — this is a single-source TI part. For BOM risk mitigation, confirm the supply channel and lead time at quote stage.
Package and footprint checklist
Housed in a 64-WQFN (9x9 mm) with an exposed thermal pad. No special MSL handling beyond standard JEDEC Level 3 is indicated, but verify the moisture sensitivity level on the latest TI packing label before reflow.