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Texas Instruments LMK04808BISQE/NOPB — Clock & Timing ICs

LMK04808BISQE/NOPB Jitter Cleaner PLL, 1.536 GHz, 2:14 ratio

MPNLMK04808BISQE/NOPB
Active

Texas Instruments PLLatinum™ jitter cleaner, PLL Yes, Type Jitter Cleaner, Input LVCMOS/LVDS/LVPECL, Output LVCMOS/LVDS/LVPECL, 1.536 GHz max, 2:14 I/O ratio, 64-WFQFN exposed pad, -40°C to 85°C.

$14.6000Ref. price · indicative, final on quote
Sourced new & surplus through independent channelsAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

LMK04808BISQE/NOPB specifications
ParameterValue
TypeJitter Cleaner
SeriesPLLatinum™
MountingSurface Mount
Voltage3.15V ~ 3.45V
Frequency1.536GHz
Operating temperature-40°C~85°C
PLLYes
InputLVCMOS, LVDS, LVPECL
OutputLVCMOS, LVDS, LVPECL
PackageTape & Reel (TR); Cut Tape (CT)
Case64-WFQFN Exposed Pad
Divider (Multiplier)Yes/No
Number of circuits1
Ratio - Input:Output2:14
Differential - Input:OutputYes/Yes

Product details

Jitter cleaner with 14-output fan-out

The Texas Instruments LMK04808BISQE/NOPB is a PLLatinum jitter cleaner that accepts LVCMOS, LVDS, or LVPECL reference inputs and delivers up to 14 differential outputs across the same logic families, with a maximum output frequency of 1.536 GHz. The 2:14 input-to-output ratio lets a single device replace a jitter attenuator plus a clock fan-out buffer, cutting the additive phase noise that comes from cascading separate stages.

1.536 GHz ceiling and I/O flexibility

The 1.536 GHz maximum output frequency covers the reference clock rates for 10 GbE SerDes, JESD204B ADC/DAC converters, and wireless base-station local oscillators. The PLL locks to a clean reference and attenuates the phase noise from the upstream oscillator, so the 14 outputs carry a jitter floor set by the PLL's own loop filter rather than the input source. Each output bank can be independently configured for LVCMOS, LVDS, or LVPECL levels, which means the same IC drives an FPGA SerDes bank (LVDS), a radio-frequency synthesizer (LVPECL), and a system clock monitor (LVCMOS) without external level translators. The differential input-to-output path (Yes/Yes) preserves common-mode rejection across the clock tree.

Listed as Active, so no last-time-buy or allocation risk. The part is in standard production and available through franchised distribution.

Frequently asked questions

What are the specifications of LMK04808BISQE/NOPB?

It is a PLL-based jitter cleaner with a 2:14 input-to-output ratio, maximum output frequency of 1.536 GHz, and support for LVCMOS, LVDS, and LVPECL on both input and output sides. The device is supplied in a 64-WFQFN exposed pad package (9x9 mm) and requires a 3.15V to 3.45V supply.