What the 6.175 GHz ceiling means for your clock tree
The LMK04610RTQT: This jitter cleaner accepts CML, LVCMOS, LVDS, and LVPECL inputs and outputs HCSL, LVDS, or LVPECL — covering most serializer/deserializer reference clocks, ADC/DAC sample clocks, and FPGA transceiver clocks without external level translation. The 6.175 GHz max frequency sets the upper bound for the cleaned output. Below that, the PLL attenuates phase noise on the reference, which is the whole point of a jitter cleaner over a generic PLL.
Supply range and package — board-level constraints
The 1.7 V to 3.465 V supply spans 1.8 V and 3.3 V rails used in most high-speed digital systems.
