2 GHz jitter cleaning for high-speed serial links
The LMK04610RTQR is a PLL-based jitter cleaner from Texas Instruments. Its 2 GHz maximum frequency covers common serial data rates for 10GbE, CPRI, and JESD204B interfaces — if your line rate is above that, this part will not lock. The 2:10 input-to-output ratio lets a single reference clock feed ten cleaned copies, saving board space by eliminating external fan-out buffers. All I/O pairs are differential, which keeps common-mode noise out of the clock path.
Multi-protocol I/O and supply flexibility
Inputs accept CML, LVCMOS, LVDS, and LVPECL; outputs drive HCSL, LVDS, and LVPECL. That means you can pair this part directly with most FPGA reference clock pins, SerDes transceivers, or ADC/DAC sample clocks without external level translators — but confirm the output swing matches your receiver's threshold, especially for HCSL which has a different common-mode than LVDS. Supply range spans 1.7 V to 3.465 V, covering 1.8 V, 2.5 V, and 3.3 V rails. If your board runs a 1.2 V core rail, you will need a separate regulator — the part does not operate below 1.7 V.