1.08 GHz PLL for high-speed clock trees
The LMK04133SQE/NOPB is a PLLatinum™ clock generator from Texas Instruments built around a single PLL core that synthesises up to 1.08 GHz. It accepts LVCMOS, LVDS, or LVPECL reference inputs and delivers six outputs in LVCMOS, LVDS, 2VPECL, or LVPECL formats — covering the common logic families used in ADC/DAC sampling clocks, FPGA reference clocks, and SerDes frame clocks. The 2:6 input-to-output ratio means two independent reference inputs feed the PLL, and six differential or single-ended outputs are available for fan-out across a board. The differential input and output capability (Yes/Yes) keeps jitter low on long traces or backplane routes.
The supply range is 3.15 V to 3.45 V — a tight 300 mV window. This forces a clean 3.3 V rail; a standard 3.3 V LDO with 2% tolerance (e.g., 3.3 V ± 66 mV) stays inside the window, but a 3.3 V rail from a switching regulator with 5% ripple may push the PLL out of spec at the low end. Budget a low-noise LDO for this rail.