Clock-tree clean-up for 1.08 GHz signal chains
The Texas Instruments LMK04110SQ/NOPB is a PLLatinum™ clock jitter cleaner that accepts LVCMOS, LVDS, or LVPECL reference inputs and delivers 2VPECL or LVPECL outputs at frequencies up to 1.08 GHz. It integrates a single PLL with a 2:5 input-to-output ratio, making it a targeted fit for cleaning up jitter on high-speed serial links, ADC/DAC sample clocks, and FPGA reference clocks in base station, test equipment, and communications infrastructure.
Which exact ordering code covers the package and temperature grade
The /NOPB suffix on this ordering code confirms lead-free / RoHS-compliant construction.
Supply rail and signal interface constraints
The supply voltage range is 3.15 V to 3.45 V — a tight 300 mV window that demands a clean, low-noise rail. The PLL accepts differential or single-ended inputs (LVCMOS, LVDS, LVPECL) and outputs differential LVPECL or 2VPECL levels, so the downstream receiver must be terminated for those logic families. The single PLL circuit includes an internal divider (Yes) but no multiplier, meaning the output frequency is a divided-down version of the VCO, not a multiplied reference.