The LMK04100SQX/NOPB is a PLLatinum-series clock jitter cleaner from Texas Instruments, integrating a phase-locked loop with a 1.08 GHz maximum frequency ceiling. That 1.08 GHz figure sets the upper bound for the VCO range — it can synthesize or clean up clocks for 10G Ethernet reference, JESD204B SYSREF, or high-speed ADC/DAC sample clocks without an external VCXO. The input stage accepts LVCMOS, LVDS, or LVPECL, and the outputs deliver LVCMOS, 2VPECL, or LVPECL with differential capability on both sides. This means the part bridges between a crystal or single-ended reference and a differential clock tree — no external level translation needed between the oscillator and the FPGA or converter clock inputs. The supply rail is tight at 3.15 V to 3.45 V, so a clean 3.3 V rail with under 50 mV ripple is assumed.
Industrial temperature grade and deployment context
The industrial range also covers most communications and data-center line cards where the ambient stays below 70°C but the local heating from adjacent ASICs pushes the board temperature higher. The single PLL circuit with a 2:7 input-to-output ratio means one reference clock can generate up to seven cleaned or multiplied outputs — typical for fanning out a 156.25 MHz reference to multiple SerDes transceivers or distributing a 122.88 MHz ADC sample clock across a multi-channel receiver array.
Active lifecycle — sourcing posture
The part ships in tape and reel (TR) for automated pick-and-place.