2.6 GHz PLL clock tree in a 1:14 fanout
The Texas Instruments LMK03806BISQ/NOPB is a clock generator with an integrated PLL that can be bypassed, delivering up to 2.6 GHz on its outputs. The 1:14 input-to-output ratio means a single reference clock fans out to fourteen independent clock domains, each programmable for frequency and format. Input accepts LVCMOS, LVDS, LVPECL, or a crystal oscillator; outputs are available in LVCMOS, LVDS, or LVPECL levels. This multi-protocol I/O eliminates external level translators when interfacing with FPGAs, SERDES, or ASICs that use different signalling standards.
Supply rail and package — what the board layout needs
The device operates from a 3.15 V to 3.45 V supply — a tight 300 mV window. The supply rail should be clean, with ripple below 10 mVpp, because PLL phase noise is directly sensitive to supply noise. A dedicated LDO per supply pin is common practice. The datasheet's recommended footprint includes a 5×5 via grid; skipping the vias raises the junction temperature by 15-20°C under full fanout load.
Temperature grade and deployment context
It fits outdoor radio units, base-station timing cards, and networking switches that sit in uncontrolled enclosures. The PLL maintains lock across the full range without external temperature compensation. This is a current-production part suitable for new designs and volume builds.