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Texas Instruments LMK03002ISQ/NOPB — Clock & Timing ICs

LMK03002ISQ/NOPB Clock Conditioner, PLL, 1.724 GHz, TI

MPNLMK03002ISQ/NOPB
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Texas Instruments LMK03002ISQ/NOPB Clock Conditioner, PLL Yes, Input LVCMOS/LVDS/LVPECL, Output LVPECL, 1.724 GHz max, 48-WFQFN exposed pad, industrial temp.

$17.3128Ref. price · indicative, final on quote
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

LMK03002ISQ/NOPB specifications
ParameterValue
TypeClock Conditioner
MountingSurface Mount
Supply voltage3.15V ~ 3.45V
Frequency - max1.724GHz
Operating temperature-40°C~85°C
PLLYes
InputLVCMOS, LVDS, LVPECL
OutputLVPECL
PackageTape & Reel (TR); Cut Tape (CT)
Case48-WFQFN Exposed Pad
Divider (Multiplier)Yes/No
Number of circuits1
Ratio - Input:Output1:4
Differential - Input:OutputYes/Yes

Product details

PLL-based clock conditioner for high-speed signal chains

The LMK03002ISQ/NOPB is a PLL-based clock conditioner from Texas Instruments that accepts LVCMOS, LVDS, or LVPECL inputs and delivers a conditioned LVPECL output up to 1.724 GHz — suitable for cleaning jitter on a reference clock feeding high-speed ADCs, DACs, or SERDES transceivers. The integrated PLL and 1:4 fanout buffer (ratio input:output 1:4) let a single device take one reference and distribute four phase-aligned LVPECL copies, reducing component count on the clock tree.

Industrial temperature range and supply voltage

Supply voltage is 3.15 V to 3.45 V, a narrow window that demands a clean 3.3 V rail with less than 5% ripple — a local LDO or pi-filter ahead of the device is typical practice.

Package, footprint, and thermal management

The exposed pad also serves as the ground return for the PLL and output drivers; a solid connection to the PCB ground plane is critical for phase-noise performance.

Frequently asked questions

Where can I buy LMK03002ISQ/NOPB and get a price?

Submit a request with your target quantity and required delivery window.

What input and output signal standards does this part support?

The input accepts LVCMOS, LVDS, or LVPECL levels; the output is LVPECL only. Both input and output are differential-capable, simplifying interface to high-speed logic families.