3.1 GHz clock distribution in a 7x7 mm QFN
It accepts LVCMOS, LVDS, LVPECL, or RF sinewave inputs and delivers LVCMOS, LVDS, or LVPECL outputs, making it a flexible clock-tree building block for high-speed ADC/DAC sampling clocks, FPGA reference distribution, or RF LO fanout.
Two circuits, 1:8 or 1:6 fanout per path
The part integrates two independent signal paths, each configurable as a 1:8 or 1:6 fanout.
48-WQFN with exposed pad — rework notes
The 48-WFQFN exposed-pad package (7x7 mm) requires a good solder joint to the board ground plane for thermal and electrical performance.
For a clock-tree component that often gets designed in for a multi-year production run, that matters — you are not chasing a sunset part.