What this clock buffer does on your board
The LMK00804BPWR is a 1:4 fanout buffer with an integrated multiplexer, accepting LVCMOS or LVTTL inputs and distributing them as HCSL, LVCMOS, LVDS, LVHSTL, LVPECL, LVTTL, or SSTL outputs. It handles clock rates up to 350 MHz, making it a fit for PCIe reference clocks, Ethernet PHY timing, or FPGA clock trees where one clean source fans out to multiple loads.
The part runs on a 3.135V to 3.465V supply — a tight 3.3V ±5 % window. That means the rail needs a regulated supply; a noisy or droopy 3.3V bus risks output jitter or duty-cycle distortion.
The 16-TSSOP package is a standard, widely stocked footprint — reels are MSL 1 (no dry-bake required before reflow) so they store well on the shelf.
16-TSSOP, 4.40 mm body width, 0.65 mm pin pitch. The narrow pitch means the layout needs a clean ground plane under the part and a 0.1 µF decoupling cap within 2 mm of each supply pin. No exposed pad — thermal relief is through the leads, so keep the copper trace width to each pin at least 0.25 mm for 3.3V rails.