No PLL — pure fanout buffer, not a clock generator
The LMK00338RTAR is a 3:9 differential fanout buffer from Texas Instruments. It contains no PLL, so it does not multiply or clean up jitter — it distributes an incoming reference clock to nine outputs with minimal additive phase noise. If your design needs frequency synthesis or spread-spectrum generation, this is the wrong part; if you need to fan out a clean PCIe or SATA reference to multiple endpoints, it is exactly the right one.
Input flexibility — seven differential standards plus crystal
The buffer accepts CML, HCSL, HSTL, LVDS, LVPECL, SSTL, and a single-ended crystal input on the primary clock path. That covers every common high-speed serial interface standard used in PCIe Gen3/Gen4, SATA, and Ethernet reference clock trees. A single BOM line item handles multi-protocol backplanes without level translators.
400 MHz ceiling — enough for Gen3, marginal for Gen5
Rated at 400 MHz maximum frequency. That comfortably covers the 100 MHz PCIe reference clock and the 125 MHz SATA reference. For PCIe Gen5 (32 GT/s) the reference is still 100 MHz, so the frequency itself is fine — but the additive jitter at that data rate needs a check against the receiver's total jitter budget. The 3:9 fan-out ratio lets one clock source drive a full root complex and its downstream ports without external repeaters.
Supply rail and temperature — 3.3 V nominal, industrial range
Operates from 3.15 V to 3.45 V — a tight 3.3 V ±4.5 % window.
That means it can be designed into new production today without planning a second-source qualification.