230 MHz PLL synthesizer with bypass — industrial temp range
Texas Instruments CDCEL949PWR is a clock/frequency synthesizer with an integrated PLL that can be bypassed for a direct feed-through path. It accepts LVCMOS or crystal inputs and delivers up to nine LVCMOS outputs, with a maximum output frequency of 230 MHz.
1.7V–1.9V supply rail — decoupling and layout
The narrow 1.7V to 1.9V supply range means the board must provide a clean, regulated 1.8V rail. Decoupling capacitors placed close to each supply pin are essential to keep PLL jitter under control at 230 MHz. Housed in a 24-TSSOP package with 0.65 mm pitch, this part requires careful fan-out on a two-layer board; a four-layer stack with a dedicated power plane simplifies routing and reduces noise coupling.
1:9 output fanout — clock distribution for multi-load systems
With a 1:9 input-to-output ratio, this synthesizer can drive nine clock loads from a single reference. The non-differential LVCMOS outputs target single-ended clock trees common in FPGA, ASIC, and processor designs.
No official successor or second-source cross-reference is published — this part is the current production choice for the clock-tree role it fills.