230 MHz PLL synthesizer with 1:9 fanout
The Texas Instruments CDCEL949PW is a PLL-based clock/frequency synthesizer that accepts an LVCMOS or crystal input and delivers nine LVCMOS outputs at up to 230 MHz. The PLL can be bypassed, letting the input clock pass through directly when you need a clean feed without multiplication or jitter accumulation from the loop.
Supply rail and output drive
The narrow 1.7 V–1.9 V supply means this part needs its own low-noise 1.8 V rail, not a shared 3.3 V or 2.5 V plane. Plan a separate LDO or switching regulator for this supply domain. All nine outputs are LVCMOS — no differential pairs — so the fanout is single-ended. The 230 MHz ceiling is the maximum toggle rate; real-world trace length and load capacitance will limit the usable frequency on a given board. The single PLL circuit (no divider on the feedback path, multiplier enabled) generates the output frequencies from the reference. With a 1:9 input-to-output ratio, one crystal or LVCMOS source feeds up to nine clock loads.
Housed in a 24-TSSOP (4.40 mm width) with a 0.65 mm pitch — a common footprint that routes out on a two-layer board without difficulty. Surface-mount only; the tube shipping medium is fine for prototype quantities, but production reels (the PWR suffix variant) are the usual pick for volume assembly.