230 MHz PLL with a 1.8 V-only rail
The CDCEL913PWRG4 is a single-circuit PLL clock synthesizer from Texas Instruments that accepts either an LVCMOS reference or a fundamental-mode crystal and delivers up to three LVCMOS clock outputs, each running to 230 MHz. The part includes a PLL bypass mode, which lets you feed the reference straight through to the outputs for system test or low-jitter paths where the PLL would add phase noise.
Supply rail and temperature — the BOM gate
If your board already carries a 1.8 V rail (common for DDR memory or low-power FPGAs), this PLL drops in without an extra regulator. If not, budget for a small LDO.
Three outputs, no differential
The 1:3 input-to-output ratio gives three LVCMOS outputs from one reference — enough to clock a small FPGA bank, a couple of SERDES transceivers, and a PHY, all from a single PLL. The outputs are single-ended only; there is no differential (LVPECL, LVDS, HCSL) output option, so this part is not suited for high-speed serial links that need a differential reference.
For a new design, this part is a low-risk choice from a lifecycle standpoint — you are not betting on a sunsetting line.