230 MHz PLL synthesizer for 1.8V clock trees
The TI CDCEL913PW is a PLL clock synthesizer with bypass capability, generating up to three LVCMOS clock outputs from a single LVCMOS or crystal reference. The PLL locks to the input and multiplies or divides it to produce output frequencies up to 230 MHz, making it suitable for clocking FPGAs, MCUs, or serial transceivers that need a clean, synthesised clock from a lower-frequency reference. If your board already has a 1.8 V rail, this part drops in without a separate regulator.
Three outputs, one reference — clock tree fit
With a 1:3 input-to-output ratio, the CDCEL913PW provides three synthesised clocks from a single crystal or LVCMOS input. The PLL includes a bypass mode that passes the input clock directly to the outputs, bypassing the PLL loop. This is useful during system bring-up to isolate PLL lock issues, or when a low-jitter reference path is needed for a specific peripheral. All outputs are LVCMOS — single-ended, not differential. If your design requires differential clocks (LVPECL, LVDS, HCSL), this part is not the right fit; you would need a synthesizer with differential outputs or add an external converter.